 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| HV440 High-Voltage Ring Generator Ordering Information Operating Voltage VPP1 - VNN1 220V Package Options SOW-16 HV440WG Features 220V maximum operating voltage Integrated high voltage transistors Up to 70 VRMS ring signal Pulse by pulse output over current protection 5 REN output capability External MOSFETs enhance output rating to 20 REN General Description The Supertex HV440 is a monolithic integrated circuit capable of generating up to 70V RMS sine wave output at frequencies of 15Hz to 60Hz with a load of 5 North American RENs. Its output rating can be enhanced to 20 North American RENs with the addition of two Supertex MOSFETs: one N-Channel MOSFET, the TN2524N8 and one P-Channel MOSFET, the TP2522N8. The high voltage output P- and N-Channel transistors are controlled independently by the logic inputs PIN and NIN. Connecting the mode pin to ground will enable the device to be controlled with a single input, NIN. This adds a 200ns deadband on the control logic to avoid cross conduction on the high voltage output. A logic high on NIN will turn the high voltage P-Channel on and the NChannel off. The high voltage outputs have pulse by pulse over current protection set by two external sense resistors. Nominal PWM logic input frequency is 100KHz. Applications Microcontroller or microprocessor controlled high voltage ring generator Set-top/Street box ring generator Pair gain ring generator Wireless local loops Fibre in the loop/to the curb Coax cable loop Pin Configuration VPP1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VPP2 PGATE VPSEN HVOUT VNSEN NGATE VNN2 VNN1 Absolute Maximum Ratings VPP1 - VNN1, power supply voltage VPP1, positive high voltage supply VPP2, positive gate voltage supply VNN1, negative high voltage supply VNN2, negative gate voltage supply VDD, logic supply Storage temperature Power dissipation +240V +120V +120V -170V -170V +7.5V -65xC to +150xC 800mW PGND GND Mode PIN NIN EN VDD Top View SOW-16 A032105 1 Electrical Characteristics (Over operating supply voltage unless otherwise specified, TA = 25C.) HV440 Min 15 VPP1 - 9.9 VPP1 - 220 4.5 250 250 Typ Max 110 VPP1 -19.1 -110 VNN1 + 10.5 5.5 400 550 150 60 1.7 1.9 1.0 25 0 4.0 1.0 5.0 Unit V V V V V A A A A mA mA mA A V V Mode = 0V VDD = 5.0V VDD = 5.0V Conditions TA = -40C to +85C TA = -40C to +85C TA = -40C to +85C TA = -40C to +85C TA = -40C to +85C PIN = NIN = 0V, TA = -40C to +85C PIN = NIN = 0V, TA = -40C to +85C PIN = NIN = 0V Mode = 0 PIN = NIN = 0V Mode = 1 No load, VOUTP and VOUTN switching at 100KHz, TA = -40C to +85C No load, VOUTP and VOUTN switching at 100KHz, TA = -40C to +85C Symbol Parameters VPP1 VPP2 VNN1 VNN2 VDD IPP1Q INN1Q IDDQ IDDQ IPP1 INN1 IDD IIL VIL VIH High voltage positive supply Positive linear regulator output voltage High voltage negative supply Logic supply voltage VPP1 quiescent current VNN1 quiescent current VDD1 quiescent current VDD1 quiescent current VPP1 operating current VNN1 operating current VDD operating current Mode logic input low current Logic input low voltage Logic input high voltage Negative linear regulator output voltage VNN1 + 5.6 High Voltage Output Symbol Parameters RSOURCE VOUTP source resistance IOUT = 100mA RSINK VOUTP sink resistance R/T Change in source/sink resistance over temperature td(ON) HVOUT delay time trise HVOUT rise time td(OFF) HVOUT delay time tfall HVOUT fall time tdb Logic deadband time Vpsen HVOUT current source sense voltage Vnsen tshortP tshortN tWHOUT tWLOUT HVOUT current sink sense voltage HVOUT off time when current source sense is activated HVOUT off time when current sink sense is activated Minimum pulse width for HVOUT at VPP1 Minimum pulse width for HVOUT at VNN1 Min Typ 60 60 0.33 150 50 200 50 200 VPP1 - 1.25 VPP1 -1.31 V TA = -40C to +85C ns ns ns ns TA = -40C to +85C TA = -40C to +85C VNN1 + 1.33 100 100 500 500 Max 80 80 Unit /C ns ns ns ns ns V IOUT = -100mA TA = -40C to +85C PIN = high to low, Mode = high PIN = high to low NIN = low to high, Mode = high NIN = low to high Mode = low TA = -40C to +85C Conditions VPP1 -0.75 VPP1 -0.67 VNN1 + 0.65 VPP1 -1.00 VNN1 + 0.75 VNN1 + 1.00 VNN1 + 1.25 Truth Table NIN L L H H L H X PIN L H L* H X X X Mode H H H H L L X EN L L L L L L H 2 HVOUT VPP1 High Z - VNN1 VNN1 VPP1 High Z 032105 *This state will short VPP1 to VNN1 and should therefore be avoided. Block Diagram VPP1 Current Sense and Driver Linear Reg Vpsen HV440 VDD PIN NIN EN Mode GND High Voltage Level Translator Pgate VPP2 HVOUT Logic VDD High Voltage Level Translator Linear Reg Current Sense and Driver PGND VNN2 Ngate Vnsen VNN1 Pin Description VPP1 VPP2 VNN1 VNN2 VDD GND PGND PIN NIN EN Mode HVOUT Vpsen Vnsen Pgate Ngate Positive high voltage supply. Positive gate voltage supply. Generated by an internal linear regulator. A 0.1F capacitor should be connected between VPP2 and VPP1. Negative high voltage supply. Negative gate voltage supply. Generated by an internal linear regulator. A 0.1F capacitor should be connected between VNN2 and VNN1. Logic supply voltage. Low voltage ground. High voltage power ground. Logic control input. When mode is high, logic input high turns OFF output high voltage P-Channel. Logic control input. When mode is high, logic input high turns ON output high voltage N-Channel. Logic enable bar input. Logic low enables IC. Logic mode input. Logic low activates 200nsec deadband. When mode is low, NIN turns on and off the high voltage N- and P-Channels. Pin is not used and should be connected to VDD or ground. High voltage output. Voltage swings from VPP1 to VNN1. Pulse by pulse over current sensing for internal P-Channel MOSFET. Pulse by pulse over current sensing for internal N-Channel MOSFET. Gate drive for external P-channel MOSFET. Gate drive for external N-channel MOSFET. 032105 3 Typical Application Circuit VPP1 4.3 High Voltage Level Translator Current Sense and Driver Linear Reg Vpsen Pgate VPP2 HVOUT Logic VDD High Voltage Level Translator Linear Reg VNN2 Ngate Current Sense and Driver PGND 1.5mH 0.1F HV440 VDD PIN NIN -Controller EN Mode GND Sine Wave Ring Output 0.22F Vnsen 4.3 VNN1 0.1F HV440 032105 4 Package Outline 16-Lead SOW (Wide Body) Package Outline (WG) 10.30x7.50mm body, 2.65mm height (max), 1.27mm pitch 16 D 1 E1 Note 1 (Index Area 0.25D x 0.75E1) 1 E L2 Gauge Plane L L1 Seating Plane Top View A h h A A2 e View B View B Note 1 Seating Plane A1 b A Side View View A-A Note 1: This chamfer feature is optional. If it is not present, then a Pin 1 identifier must be located in the index area indicated.The Pin 1 identifier may be either a mold, or an embedded metal or marked feature. Symbol MIN Dimension NOM (mm) MAX A 2.15 2.65 A1 0.10 0.30 A2 2.05 2.55 b 0.31 0.51 D 10.10 10.30 10.50 E 9.97 10.30 10.63 E1 7.40 7.50 7.60 e 1.27 BSC h 0.25 0.75 L 0.40 1.27 L1 1.40 REF L2 0.25 BSC 0O 8 O 1 5O 15O JEDEC Registration MS-013, Variation AA, Issue E, Sep. 2005. Drawings are not to scale. Doc. #: DSPD-16SOWWG B032607 |
Price & Availability of HV440
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |